A parallel algorithm of correlation processing and its hardware architecture realization

A digital correlator with high speed, high precision and long sample is necessary for rader, sonar and earthquake reseach. With the development of new programmable digital signal processing (DSP) chip,this need is becoming content. In this paper, a parallel algorithm with pipeline architecture for long sample digital correlation is proposed and realized by high speed DSP device. The speed and precision of this kind of algorithm is ensured by DSP's Performance. Some experiments show that the algorithm is of universal significance. Lastly, as an example, the hardware architecture and software flow scheme of 1024 points digital correlator made of multichip TMS320C25 are given.