Abstract: This paper describes a VLSI architecture used for implementation of FFT,of which the computation cell (CC)implement the computation of 4-point DFT and multiplication of rotate factors using radix-4 pipeline computation method,and the address generator (AG) gives the addresses of both data and rotate factors simultaneously. In addition,this paper also presents the recursive and cascade circuit structures using the CC and AG. Up to 64k-point FFT can be computed quickly and flexibly by using these two circuit structures.